Concurrent Fault Detection for Secure QDI Asynchronous Circuits
نویسندگان
چکیده
Asynchronous micropipelined designs are self-checking against permanent stuck-at faults making the circuits highly resistant against invasive fault attacks. A single transient fault, however, can result in a data token insertion or deletion which can cause a continuous stream of erroneous outputs that can be exploited by a malicious attacker. We propose a system level error detection method targeted for detection of faults that cause data token insertions and deletions. The method is based on minimum distance robust error detecting codes and exploits the repeating errors in linear networks to improve the error detection performance.
منابع مشابه
Testable Design of Template based QDI Asynchronous Circuits
Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuit is accepted as an effective way to decrease complexity of design of asynchronous circuit. One of the popular pre-designed templates that most synthesis tools use it to synthesis QDI asynchronous circuit is Pre-Charged Full...
متن کاملAnalysis of delay caused by Resistive Bridging faults in Secured CMOS 45 nm Technology, Implemented in QDI GHANIA AIT ABDELMALEK, REZKI ZIANI and MOURAD LAGHROUCHE
The article focuses on the defects modeling of secured CMOS circuits, implemented in Quasi Delay Insensitive (QDI). We analyze the static and the dynamic behavior of resistive bridges as a function of its unpredictable resistance. SPICE simulations were performed for 45nm CMOS technology. Simulation results are given for the conditions of defect detection and for the delay induced by the resist...
متن کاملProtecting QDI interconnects from transient faults using delay-insensitive redundant check codes
Asynchronous circuit design is a promising technology for large-scale multi-core systems. As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to delay variations. However, QDI interconnects are vulnerable to faults. Traditional fault-tolerant techniques for synchronous circuits cannot be...
متن کاملImproving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals
The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data processing times. The efficiency of the counter...
متن کاملA Secure Asynchronous Hardware Implementation Of DES Cryptography Algorithm
QDI Dual-rail asynchronous circuits, if implemented carefully balanced, have natural and efficient resistance to side-channel attacks in cryptography applications. Due to hardware redundancy in previous balanced gate designs, there are many faults which can make them imbalanced without causing logical errors. Therefore, traditional logical testing methods are unable to test and verify if a gate...
متن کامل